The present invention relates to the field of integrated circuits and their operation. More specifically, in one embodiment the invention provides an interconnect chip to couple a plurality of programmable logic devices to each other.
Logic devices and methods of their operation are well known to those of skill in the art. Programmable logic devices have found particularly wide application as a result of their combined low up-front cost and versatility to the user.
Altera""s FLEX(copyright) and MAX(copyright) lines of programmable logic are among the most advanced and successful programmable logic devices. In the FLEX(copyright) 8000 logic devices, for example, a large matrix of logic elements (LEs) is utilized. In one commercial embodiment of such devices, each LE includes a 4-input look-up table for performance of combinational logic (e.g., AND, OR, NOT, XOR, NAND, NOR, and many others) and a register that provides sequential logic features.
The LEs are arranged in groups of, for example, eight to form larger logic array blocks (LABs). The LABs contain, among other things, a common interconnection structure. The various LABs are arranged in a two-dimensional array, with the various LABs connectable to each other and to pins of the device though continuous lines that run the entire length/width of the device. These lines are referred to as row interconnect (GH) and column interconnect (GV) or xe2x80x9cglobalxe2x80x9d interconnect lines.
The MAX(copyright) 7000 logic devices by way of contrast utilize what are commonly referred to as xe2x80x9cmacrocellsxe2x80x9d (analogous to LEs) as a basic logic element. The macrocells are arranged in groups of, for example, sixteen to form larger logic array blocks (LABs). A programmable interconnect array (PIA) selectively links together the multiple LABs. The PIA is a global bus that is fed by all dedicated inputs, I/O pins, and the various macrocells. The PIA is analogous to global interconnect, GHs and GVs. For example, the PIA may be fed by signals that will be used as logic inputs, global controls for secondary register functions in the LABs, input paths from I/O pins to registers that are used for setup of the device, etc.
Inputs to the LABs include inputs from pins (via I/O control blocks), the PIA, and various control (e.g. clock) pins. Logic inputs are provided to one or more of five AND devices, the outputs of which are provided to a product term select matrix. The product term select matrix selects which inputs will be provided to an OR or XOR function, or as secondary inputs to registers in the macrocell. Product terms may be shared between macrocells for complex logic functions. Outputs from the LABs are provided to the I/O control block to the PIA and/or various output pins.
The FLEX(copyright) and MAX(copyright) programmable logic devices have met with substantial success and are considered pioneering in the area of programmable logic. In fact, designers are increasingly using multiple FLEX(copyright) and MAX(copyright) devices, or even an entire array of programmable logic devices, to implement functions that are too large to be supported by a single programmable logic device. For example, it would be quite typical for a hardware designer to emulate a complex system in an array of programmable logic devices as a prototype before implementing the tested design in an application specific integrated circuit (ASIC) for production. In order to use multiple devices, the designer must find ways to overcome several hurdles, including partitioning the design into smaller portions to be parceled out among the multiple devices, finding an optimum placement for the multiple devices on a circuit board, and routing the connections between devices.
These steps need to be repeated each time there is a change in the system design. Currently, there is partitioning software that breaks a design up into smaller pieces in a logical manner to divide the design among several programmable logic devices. However, the other tasks of placing and routing among devices are left to the user of the devices. When using a single programmable logic device, the user may simply leave the tasks of placing and routing logic cells to the appropriate routing software, such as, for example, Altera""s MAXPlus+(copyright) software package. But on a system level, there is currently no such device or software to ease the job of the designer in a similar fashion.
Thus, a need clearly exists for a device to interconnect multiple programmable logic devices that does not place the entire burden on the user.
The present invention provides a method and apparatus for interconnecting multiple programmable logic devices. In a preferred embodiment of the invention, an interconnect chip couples one programmable logic device to another programmable logic device. The interface between devices takes place within the interconnect chip, which can be configured using available routing software, thereby sparing the user the task of routing the connections between devices on the board.
A further understanding of the nature and advantages of the inventions herein may be realized by reference to the remaining portions of the specification and the attached drawings.